This invention relates to static random access memory devices, commonly termed SRAMs. SRAMs are currently used in a wide variety of applications requiring relatively fast memory, such as cache memory applications. A typical smaller capacity SRAM (64K bit density or less) includes a plurality of individual memory cells, typically implemented as four insulated gate transistors and load resistors and associated logic for providing row and column addressing, data input buffering and write drivers, output sense amplifiers and output buffers. Each individual memory cell is accessed directly by row and column decoding to activate the word lines and to select the bit lines in the array, and write and read operations are performed using the data input buffer and write driver circuitry (for a write operation) and the sense amplifier and output buffer circuitry (for a read operation). This approach can be defined as the streamlined approach to SRAM organization and operation.
As processor speeds increase, along with the demand for SRAMs of ever increasing memory capacity with access times compatible with the faster processors, the physical limit of the original SRAM design using the streamlined approach is reached. As a consequence, the SRAM architecture has been modified by what is commonly termed the modular approach employing a local block sense amplifier along with an output sense amplifier. In the modular architecture, typically found in SRAMs having a density of 256K bit or larger, the memory cells are arranged in smaller blocks than the full matrix size, and each block is provided with a complete set of associated logic. With reference to FIG. 1, which is a diagram of an SRAM using this modular approach, each memory block 12 has associated block word line select logic 14, column select logic 16, block sense amplifiers 18, block write drivers 20 and other block logic 22. The individual blocks and the individual memory cells within each block are addressed by means of row and block address buffers 24, row and block decoders 25, column and block address buffers 26, and column and block decoders 27 which receive row, column and block address information via an address bus (not shown). Each individual block word line 14 is coupled to main data lines 30 which provide interconnection between the individual memory blocks 12 and the input/output data circuitry generally designated with reference numeral 35 and which includes a plurality of data input buffers 36, write data drivers 38, output sense amplifiers 40 and data output buffers 42. FIG. 2 is a more detailed view of the control circuitry for a single memory block 12. As seen in this figure, each memory block 12 includes a plurality of bit lines 50 and complementary bit lines 51, and a plurality of word lines 52, to which selected ones of individual memory cells 55 are coupled. The column select and block word line select circuitry 16, 14 are located within the memory block 12, as are the individual block write circuit 20, block sense amplifiers 18 and block logic 22. Access to individual memory cells 55 in a given memory block 12 requires both the local read/write circuitry 18, 20 and 22 termed the secondary read/write circuitry, as well as the relatively remote (but still on the chip) primary read/write circuitry 36, 38, 40 and 42. Thus, even though the modular architecture provides relatively fast access compatible with high speed processors (access times of 20 nanoseconds or less) with relatively large storage capacity (256K bits or greater), this relatively fast access and large storage capacity is achieved only at the penalty of requiring a relatively large number of active secondary read/write circuits closely adjacent the individual memory cells of a given memory block in addition to the primary chip read/write circuits in the input/output data circuitry. As a consequence, the size of an SRAM using the modular architecture is substantially larger than normally desirable, and the inclusion of a relatively large number of secondary read/write circuits and control logic tends to decrease the yield of usable SRAM integrated circuits from a given wafer and thus increases the per unit die cost.